1. Field of the Invention
The present invention relates to a method for erasing flash memory, and more particularly, to a method for erasing flash memory without over erasing.
2. Description of the Related Art
In order to change data of the flash memory, the data within the flash memory should be erased first and then reprogrammed. U.S. Pat. No. 7,130,240 discloses a method for erasing sectors of a flash memory in sequence. However, such method is time-consuming and will not fulfill the current needs of the industry.
In addition, as the memory capacity of the flash memory increases, the time needed to erase will increase. To solve such problem, a technique for simultaneously erasing the selected memory blocks is required. However, the well-known issue of “slow bits” residing in each sector, which represent unsuccessfully erased bits after an erasing action, tend to slow down the entire process and reduce the reliability of the flash memory. The slow bits need greater than normal durations of erasing action to completely erase. At the same time, caution is needed to avoid other normal bits being redundantly erased, or “over erased.” If normal bits are over erased, more time is needed to correct them, and sometimes it is impossible to recover data lost due to heavily over-erased sectors. U.S. Pat. No. 5,841,721 discloses a method to verify whether the erasure is successfully performed. To avoid over erasing, this method verifies the multiple sectors after one erasing action. However, this method will naturally consume a lot of time on erasing verification. For example, there is a flag for each block, and the flag indicates if the block is selected for erasure. Erasure is performed on all selected blocks that do not pass verification. However, if the selected block passes verification, the flag is reset and no further erasure is performed on this block. Verification is then performed on all selected and unsuccessfully erased blocks. If subsequent blocks pass verification, their flags are reset, and no further erasure is performed on these blocks.
U.S. Pat. No. 5,954,828 and U.S. Pat. No. 6,222,772 disclose another type of erasing methodology, which allows a number of failing bits and therefore some slow bits can be ignored. However, such method can only be applied on fault tolerant applications.